Bipolar transistor

ABSTRACT

A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.

FIELD OF THE INVENTION

This invention concerns a bipolar transistor which can be, inparticular, in the form of a self-aligned bipolar transistor.

BACKGROUND

In the case of bipolar transistors, the extrinsic base resistance, withthe transition frequency and base collector capacitance, is one of thedecisive transistor parameters which determine important characteristicquantities such as the maximum oscillation frequency, the amplification(“gain”), the minimum noise factor, gate delay times, etc. of thebipolar transistor. The extrinsic base resistance corresponds to theresistance between the base, or the actual base area, and an externalcontact, which is connected to the base via a connecting line.

Regarding the above-mentioned transistor parameters, the followingapplies, for instance, to the maximum oscillation frequency +71 _(max)of the bipolar transistor: $\begin{matrix}{f_{\max} \approx \sqrt{\frac{f_{T}}{8{\pi \cdot R_{B} \cdot C_{BC}}}}} & (1)\end{matrix}$where +71 _(T) is the transition frequency, R_(B) is the extrinsic baseresistance and C_(BC) is the base collector capacitance of the bipolartransistor.

For the minimum noise factor F_(min) of a bipolar transistor, thefollowing applies, depending on the extrinsic base resistance R_(B) andfrequency +71: $\begin{matrix}{F_{\min} \approx {1 + \frac{1}{\beta} + {\frac{f}{F_{T}} \cdot \sqrt{{\frac{2 \cdot I_{C}}{V_{T}} \cdot R_{B} \cdot \left( {1 + \frac{f_{T}^{2}}{\beta \cdot f^{2}}} \right)} + \frac{f_{T}^{2}}{\beta \cdot f^{2}}}}}} & (2)\end{matrix}$where β is the small signal current amplification, I_(C) is thecollector current, and V_(T) is the thermal voltage of the bipolartransistor.

From the two formulae (1) and (2), it can be seen that the extrinsicbase resistance R_(B) should be small for fast switching and low noisefactors. One method of reducing losses in the case of bipolartransistors is the use of a polysilicon electrode for contacting thebase. A p⁺ polysilicon layer provides a low-resistance path withcorrespondingly low capacitance for the base current.

Specially small extrinsic base resistances can be achieved, forinstance, by use of the concept of the so-called “self-aligned doublepolysilicon bipolar transistor”, as described in “Self-Aligned BipolarTransistors for High-Performance and Low-Power-Delay VLSI”, T. H. Ninget al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, pp.1010-1013, 1981. This concept is therefore used in almost all widelyused production technologies for ultra-high frequency bipolartransistors.

SUMMARY

The present invention provides a bipolar transistor. Embodiments of theinvention provide a bipolar transistor and method of making a bipolartransistor. In one embodiment, the invention provides a bipolartransistor having a polysilicon layer into which impurity atoms areinserted, thereby reducing the layer resistance.

In the attached FIG. 1, such a self-aligned npn double polysiliconbipolar transistor is shown in cross-section. The emitter 3 is contactedvia an n+ doped polysilicon electrode 1. A p+ polysilicon electrode 2 isassigned to the p+ doped base 4. The self-aligned emitter baseinsulation 7 is called the “spacers”. Additionally, under the emitterelectrode 3 a TEOS (“tetraethoxysilan/tetraethylorthosilicate”)insulation layer 6 is provided, and under the base electrode 2 a LOCOS(“local oxidation of silicon”) insulation layer 8 is provided. In thefigure, the collector area 5 of the bipolar transistor (without theassociated collector electrode) is also shown by a dashed line. A methodof producing such a bipolar transistor is described, for instance, inEP-B1-0 535 350.

In the case of a self-aligned double polysilicon bipolar transistor suchas is shown in the figure, the extrinsic base resistance R_(B) consistsessentially of three parts, which are called below the “internal”resistance part R_(Bi), the “external” resistance part R_(Be), and the“link” resistance part R_(Bl). The internal resistance part R_(Bi)results from the resistance in the base area 4 on the active transistorarea. The external resistance part R_(Be) describes the resistance ofthe polysilicon base electrode 2, which leads to the external basecontact. The link resistance part R_(Bl) represents the extrinsic baseresistance which results from the low-doped zone under the self-alignedemitter base insulation, the spacers 7.

In today's bipolar transistors, the total extrinsic base resistanceR_(B) is usually dominated by the sum of the internal resistance partR_(Bi) and the link resistance part R_(Bl). Because of progressinglateral scaling of the components, the internal resistance part R_(Bi)and the link resistance part R_(Bl) are continually being reduced.Simultaneously, the external resistance part R_(Be) is constantlyincreasing, because the vertical component scaling which is linked tothe lateral scaling requires ever thinner polysilicon layers asconnecting electrodes, and the layer resistance of these connectingareas is thus constantly increasing. Thus the external resistance partR_(Be) is becoming ever more important for the total extrinsic baseresistance R_(B).

To keep the layer resistance of the base electrode 2 as small aspossible, in general polysilicon layers doped with boron are used. Theboron doping is chosen to be above the electrically activatableconcentration of typically greater than 5×10²⁰ cm⁻³, to achieve thesmallest possible layer resistance. The boron doping atom is chosenbecause of the consideration that boron has little or no effect on thegrain growth, and does not tend to separate at the grain boundariesduring thermal processing events. The model of doping materialseparation assumes that the conductivity is controlled by separation ofdoping atoms at the grain boundaries, where the atoms are themselvescaptured and become electrically inactive. Additionally, a high dopingmaterial concentration at the grain boundaries suppresses grain growthduring annealing. Redistribution of implanted doping materials andgreater grain sizes during subsequent annealing steps change theelectrical and structural properties of the layers, which clearlyaffects the external resistance part R_(Be) of the extrinsic baseresistance R_(B). The main problem is the annealing behaviour of Sisamples with doping atoms. In fact, only a small proportion of thedoping atoms, about 10%, is ionised. It is assumed that inactive,non-eliminated doping atoms are present in cluster form. Clusterformation of the doping atoms takes place at the annealing temperature,or alternatively mainly during cooling of the sample. With typicaldoping values of boron greater than 5×10²⁰ cm⁻³ and a layer thickness of150-250 nm, minimum layer resistances of about 50-100 Ω/□ can beachieved.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in more detail below, referring to the onlyfigure of a preferred embodiment.

FIG. 1 is a cross-section illustrating one exemplary embodiment of abipolar transistor according to the invention.

DETAILED DESCRIPTION

The present invention provides a bipolar transistor in which the layerresistance of the connecting electrodes, particularly the baseelectrode, is further reduced.

According to one embodiment of the invention, it is proposed that inbipolar transistors, instead of traditional polysilicon electrodes,polysilicon layers into which impurity atoms are inserted should beused. These cause a high density of vacancies in the electrode material.

As impurity atoms, preferably C, P or Ar atoms are used, C atoms beingspecially preferred. The density of the impurity atoms in thepolysilicon layer is preferably in the range of about 10¹⁹-10²¹ cm⁻³.

Carbon with high solubility in silicon can be built into the siliconlattice at the interstices and also at the more favourable (in energyterms) lattice sites, in exchange for a Si atom. The C atoms at thelattice sites capture Si atoms which are present at interstices, andthus form bound interstitial complexes. Because of this capturingmechanism of the C atoms, additional vacancies are generated. The carbonin the polysilicon layer therefore provides sinks for interstices duringannealing, so that interstice-driven cluster formation of, for instance,boron doping atoms is suppressed, and thus the quantity andconcentration of active doping atoms can be increased. This results in alower layer resistance of the polysilicon layer which is doped with, forinstance, boron, and thus to a smaller extrinsic base resistance. Thiseffect can be further increased by the use of polysilicon layers ofpolycrystalline silicon-germanium.

Since carbon is in general use in semiconductor technology, and can beinserted into the polysilicon layer of the electrodes both directlyduring layer growth and by ion implantation, the concept of theinvention, as described above, can be implemented simply andeconomically in manufacturing methods for traditional bipolartransistors.

A further advantage is that C atoms can be built in without essentiallyinterfering with the Si lattice structure, since the volume of even SiCis only about 3% greater than that of pure Si.

Although this invention refers in particular to bipolar transistors, inprinciple use with other transistor types such as FET, MOS or CMOStransistors is also conceivable.

The emitter 3 of the bipolar transistor is contacted via an n+ dopedpolysilicon electrode 1, and a p+ polysilicon electrode 2 is assigned tothe p+ doped base 4. Spacers 7 are provided as the self-aligned emitterbase insulation. Additionally, under the emitter electrode 1 a TEOSinsulation layer 6 is provided, and under the base electrode 2 a LOCOSinsulation layer 8 is provided. In FIG. 1, the collector area 5 of thebipolar transistor is also illustrated by a dashed line.

As the base electrode 2, a polysilicon layer, into which C impurityatoms are inserted with a concentration of 10¹⁹-10²¹ cm⁻¹, is used. Thiscan be done either by ion implantation or alternatively directly duringlayer growth, without an additional implantation step. Additionally, asalready known, the polysilicon layer is doped with boron atoms at aconcentration of greater than 5×10²⁰ cm⁻³.

The C impurity atoms incorporate themselves into the Si lattice atinterstices and preferably at the more favourable (in energy terms)lattice sites. The C impurity atoms on the lattice sites capture Siatoms from interstices and form bound interstitial complexes. Because ofthese captured Si atoms, additional vacancies are formed, with anestimated density of about 10¹⁹ cm⁻³. The Si—C agglomerates which areformed in this way are stable to about 700° C. At higher temperatures,they are converted to β SiC. The volume of SiC, which is greater byabout 3% compared with the Si matrix, can also easily be compensated forby vacancies, so that no undesired voltages occur in the electrodes. Inthis way, during annealing, the carbon generates sinks for intersticesin the polysilicon layer, so that interstice-driven cluster formation ofthe boron doping atoms is suppressed and thus the quantity of activedoping atoms can be increased.

The higher concentration of active doping atoms which is generated inthis way results in a lower layer resistance of the polysilicon layer,which is doped with boron, and thus to a smaller extrinsic baseresistance. This effect can be further increased by the use ofpolysilicon layers of polycrystalline silicon-germanium.

Obviously, alternatively or additionally to the base electrode 2, theemitter electrode 1 and the collector electrode can be in the formaccording to the invention.

Description

Bipolar Transistor

This invention concerns a bipolar transistor which can be, inparticular, in the form of a so-called self-aligned bipolar transistor.

In the case of bipolar transistors, the so-called extrinsic baseresistance, with the transition frequency and base collectorcapacitance, is one of the decisive transistor parameters whichdetermine important characteristic quantities such as the maximumoscillation frequency, the amplification (“gain”), the minimum noisefactor, gate delay times, etc. of the bipolar transistor. The extrinsicbase resistance corresponds to the resistance between the base, or theactual base area, and an external contact, which is connected to thebase via a connecting line.

Regarding the above-mentioned transistor parameters, the followingapplies, for instance, to the maximum oscillation frequency f_(max) ofthe bipolar transistor: $\begin{matrix}{f_{\max} \approx \sqrt{\frac{f_{T}}{8{\pi \cdot R_{B} \cdot C_{BC}}}}} & (1)\end{matrix}$where f_(T) is the transition frequency, R_(B) is the extrinsic baseresistance and C_(BC) is the base collector capacitance of the bipolartransistor.

For the minimum noise factor F_(min) of a bipolar transistor, thefollowing applies, depending on the extrinsic base resistance R_(B) andfrequency f: $\begin{matrix}{F_{\min} \approx {1 + \frac{1}{\beta} + {\frac{f}{F_{T}} \cdot \sqrt{{\frac{2 \cdot I_{C}}{V_{T}} \cdot R_{B} \cdot \left( {1 + \frac{f_{T}^{2}}{\beta \cdot f^{2}}} \right)} + \frac{f_{T}^{2}}{\beta \cdot f^{2}}}}}} & (2)\end{matrix}$where β is the small signal current amplification, I_(C) is thecollector current, and V_(T) is the thermal voltage of the bipolartransistor.

From the two formulae (1) and (2), it can be seen that the extrinsicbase resistance R_(B) should be small for fast switching and low noisefactors. One method of reducing losses in the case of bipolartransistors is the use of a polysilicon electrode for contacting thebase. A p⁺ polysilicon layer provides a low-resistance path withcorrespondingly low capacitance for the base current.

Specially small extrinsic base resistances can be achieved, forinstance, by use of the concept of the so-called “self-aligned doublepolysilicon bipolar transistor”, as described in “Self-Aligned BipolarTransistors for High-Performance and Low-Power-Delay VLSI”, T. H. Ninget al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, pp.1010-1013, 1981. This concept is therefore used in almost all widelyused production technologies for ultra-high frequency bipolartransistors.

In the attached figure, such a self-aligned npn double polysiliconbipolar transistor is shown in cross-section. The emitter 3 is contactedvia an n+ doped polysilicon electrode 1. A p+ polysilicon electrode 2 isassigned to the p+ doped base 4. The self-aligned emitter baseinsulation 7 is called the “spacers”. Additionally, under the emitterelectrode 3 a TEOS (“tetraethoxysilan/tetraethylorthosilicate”)insulation layer 6 is provided, and under the base electrode 2 a LOCOS(“local oxidation of silicon”) insulation layer 8 is provided. In thefigure, the collector area 5 of the bipolar transistor (without theassociated collector electrode) is also shown by a dashed line. A methodof producing such a bipolar transistor is described, for instance, inEP-B1-0 535 350.

In the case of a self-aligned double polysilicon bipolar transistor suchas is shown in the figure, the extrinsic base resistance R_(B) consistsessentially of three parts, which are called below the “internal”resistance part R_(Bi), the “external” resistance part R_(Be), and the“link” resistance part R_(Bl). The internal resistance part R_(Bi)results from the resistance in the base area 4 on the active transistorarea. The external resistance part R_(Be) describes the resistance ofthe polysilicon base electrode 2, which leads to the external basecontact. The link resistance part R_(Bl) represents the extrinsic baseresistance which results from the low-doped zone under the self-alignedemitter base insulation, the spacers 7.

In today's bipolar transistors, the total extrinsic base resistanceR_(B) is usually dominated by the sum of the internal resistance partR_(Bi) and the link resistance part R_(Bl). Because of progressinglateral scaling of the components, the internal resistance part R_(Bi)and the link resistance part R_(Bl) are continually being reduced.Simultaneously, the external resistance part R_(Be) is constantlyincreasing, because the vertical component scaling which is linked tothe lateral scaling requires ever thinner polysilicon layers asconnecting electrodes, and the layer resistance of these connectingareas is thus constantly increasing. Thus the external resistance partR_(Be) is becoming ever more important for the total extrinsic baseresistance R_(B).

To keep the layer resistance of the base electrode 2 as small aspossible, in general polysilicon layers doped with boron are used. Theboron doping is chosen to be above the electrically activatableconcentration of typically greater than 5×10²⁰ cm⁻³, to achieve thesmallest possible layer resistance. The boron doping atom is chosenbecause of the consideration that boron has little or no effect on thegrain growth, and does not tend to separate at the grain boundariesduring thermal processing events. The model of doping materialseparation assumes that the conductivity is controlled by separation ofdoping atoms at the grain boundaries, where the atoms are themselvescaptured and become electrically inactive. Additionally, a high dopingmaterial concentration at the grain boundaries suppresses grain growthduring annealing. Redistribution of implanted doping materials andgreater grain sizes during subsequent annealing steps change theelectrical and structural properties of the layers, which clearlyaffects the external resistance part R_(Be) of the extrinsic baseresistance R_(B). The main problem is the annealing behaviour of Sisamples with doping atoms. In fact, only a small proportion of thedoping atoms, about 10%, is ionised. It is assumed that inactive,non-eliminated doping atoms are present in cluster form. Clusterformation of the doping atoms takes place at the annealing temperature,or alternatively mainly during cooling of the sample. With typicaldoping values of boron greater than 5×10²⁰ cm⁻³ and a layer thickness of150-250 nm, minimum layer resistances of about 50-100 Ω/□ can beachieved.

The present invention is based on the object of providing a bipolartransistor in which the layer resistance of the connecting electrodes,particularly the base electrode, is further reduced.

This object is achieved according to the invention by a bipolartransistor with the features of claim 1. In the subclaims, preferred andadvantageous embodiments of this invention are given.

According to the invention, it is proposed that in bipolar transistors,instead of traditional polysilicon electrodes, polysilicon layers intowhich impurity atoms are inserted should be used. These cause a highdensity of vacancies in the electrode material.

As impurity atoms, preferably C, P or Ar atoms are used, C atoms beingspecially preferred. The density of the impurity atoms in thepolysilicon layer is preferably in the range of about 10¹⁹-10²¹ cm⁻³.

Carbon with high solubility in silicon can be built into the siliconlattice at the interstices and also at the more favourable (in energyterms) lattice sites, in exchange for a Si atom. The C atoms at thelattice sites capture Si atoms which are present at interstices, andthus form bound interstitial complexes. Because of this capturingmechanism of the C atoms, additional vacancies are generated. The carbonin the polysilicon layer therefore provides sinks for interstices duringannealing, so that interstice-driven cluster formation of, for instance,boron doping atoms is suppressed, and thus the quantity andconcentration of active doping atoms can be increased. This results in alower layer resistance of the polysilicon layer which is doped with, forinstance, boron, and thus to a smaller extrinsic base resistance. Thiseffect can be further increased by the use of polysilicon layers ofpolycrystalline silicon-germanium.

Since carbon is in general use in semiconductor technology, and can beinserted into the polysilicon layer of the electrodes both directlyduring layer growth and by ion implantation, the concept of theinvention, as described above, can be implemented simply andeconomically in manufacturing methods for traditional bipolartransistors.

A further advantage is that C atoms can be built in without essentiallyinterfering with the Si lattice structure, since the volume of even SiCis only about 3% greater than that of pure Si.

Although this invention refers in particular to bipolar transistors, inprinciple use with other transistor types such as FET, MOS or CMOStransistors is also conceivable.

The invention is explained in more detail below, referring to the onlyfigure of a preferred embodiment.

Regarding the embodiment which is shown in the figure, to avoidrepetition reference can be made to a large extent to the aboveexplanation of the prior art. As mentioned above, in the figure aself-aligned npn bipolar transistor is shown in cross-section.

The emitter 3 of the bipolar transistor is contacted via an n+ dopedpolysilicon electrode 1, and a p+ polysilicon electrode 2 is assigned tothe p+ doped base 4. Spacers 7 are provided as the self-aligned emitterbase insulation. Additionally, under the emitter electrode 1 a TEOSinsulation layer 6 is provided, and under the base electrode 2 a LOCOSinsulation layer 8 is provided. In the figure, the collector area 5 ofthe bipolar transistor is also shown by a dashed line.

As the base electrode 2, a polysilicon layer, into which C impurityatoms are inserted with a concentration of 10¹⁹-10²¹ cm⁻³, is used. Thiscan be done either by ion implantation or alternatively directly duringlayer growth, without an additional implantation step. Additionally, asalready known, the polysilicon layer is doped with boron atoms at aconcentration of greater than 5×10²⁰ cm⁻³.

The C impurity atoms incorporate themselves into the Si lattice atinterstices and preferably at the more favourable (in energy terms)lattice sites. The C impurity atoms on the lattice sites capture Siatoms from interstices and form bound interstitial complexes. Because ofthese captured Si atoms, additional vacancies are formed, with anestimated density of about 10¹⁹ cm⁻³. The Si—C agglomerates which areformed in this way are stable to about 700° C. At higher temperatures,they are converted to β SiC. The volume of SiC, which is greater byabout 3% compared with the Si matrix, can also easily be compensated forby vacancies, so that no undesired voltages occur in the electrodes. Inthis way, during annealing, the carbon generates sinks for intersticesin the polysilicon layer, so that interstice-driven cluster formation ofthe boron doping atoms is suppressed and thus the quantity of activedoping atoms can be increased.

The higher concentration of active doping atoms which is generated inthis way results in a lower layer resistance of the polysilicon layer,which is doped with boron, and thus to a smaller extrinsic baseresistance. This effect can be further increased by the use ofpolysilicon layers of polycrystalline silicon-germanium.

Obviously, alternatively or additionally to the base electrode 2, theemitter electrode 1 and the collector electrode can be in the formaccording to the invention.

1.-8. (canceled)
 9. A bipolar transistor comprising: an emitter area which can be contacted electrically via an emitter electrode; a base area which can be contacted electrically via a base electrode; a collector area which can be contacted electrically via a collector electrode; and wherein at least one electrode of the emitter electrode, base electrode and collector electrode is a polysilicon layer, into which impurity atoms, which cause a high density of vacancies in the polysilicon layer, are inserted.
 10. The transistor of claim 9, comprising wherein the impurity atoms are C, P or Ar atoms.
 11. The transistor of claim 9, comprising wherein the density of the impurity atoms in the polysilicon layer is in the range of about 10¹⁹ to 10²¹ cm⁻³.
 12. The transistor of claim 9, comprising wherein the polysilicon layer is doped with boron atoms.
 13. The transistor of claim 12, comprising wherein the concentration of the boron atoms is greater than 5×10²⁰ cm⁻³.
 14. The transistor of claim 9, comprising wherein the at least one electrode consists of polycrystalline silicon-germanium.
 15. The transistor of claim 9, comprising wherein the at least one electrode is the base electrode.
 16. The transistor of claim 9, comprising wherein the bipolar transistor is a self-aligned bipolar transistor.
 17. A bipolar transistor comprising: an emitter area; a base area; a collector area; and a base electrode comprising a polysilicon layer, into which impurity atoms, which cause a high density of vacancies in the polysilicon layer, are inserted.
 18. The transistor of claim 17, comprising wherein the impurity atoms are C, P or Ar atoms.
 19. The transistor of claim 17, comprising wherein the density of the impurity atoms in the polysilicon layer is in the range of about 10¹⁹ to 10²¹ cm⁻³.
 20. The transistor of claim 17, comprising wherein the polysilicon layer is doped with boron atoms.
 21. The transistor of claim 20, comprising wherein the concentration of the boron atoms is greater than 5×10²⁰ cm⁻³.
 22. The transistor of claim 17, comprising wherein the at least one electrode consists of polycrystalline silicon-germanium.
 23. The transistor of claim 17, comprising wherein the bipolar transistor is a self-aligned bipolar transistor.
 24. A bipolar transistor comprising: an emitter area which can be contacted electrically via an emitter electrode; a base area which can be contacted electrically via a base electrode; a collector area which can be contacted electrically via a collector electrode; and wherein at least one electrode of the emitter electrode, base electrode and collector electrode is a polysilicon layer, into which impurity atoms, which cause a high density of vacancies in the polysilicon layer, are inserted, wherein the impurity atoms are C, P or Ar atoms, and wherein the density of the impurity atoms in the polysilicon layer is in the range of about 10¹⁹ to 10²¹ cm⁻³.
 25. The transistor of claim 24, comprising wherein the polysilicon layer is doped with boron atoms.
 26. The transistor of claim 25, comprising wherein the concentration of the boron atoms is greater than 5×10²⁰ cm⁻³.
 27. The transistor of claim 26, comprising wherein the at least one electrode consists of polycrystalline silicon-germanium.
 28. The transistor of claim 27, comprising wherein the at least one electrode is the base electrode.
 29. The transistor of claim 28, comprising wherein the bipolar transistor is a self-aligned bipolar transistor.
 30. A bipolar transistor comprising: an emitter area; a base area; a collector area; and electrode means comprising a polysilicon layer, into which impurity atoms, which cause a high density of vacancies in the polysilicon layer, are inserted.
 31. The transistor of claim 30, comprising wherein the impurity atoms are C, P or Ar atoms.
 32. The transistor of claim 34, comprising wherein the density of the impurity atoms in the polysilicon layer is in the range of about 10¹⁹ to 10²¹ cm⁻³. 